module Register_32bit(clk, rst, d, q, sel);
input clk;
input rst;
input [31:0] d;
output [31:0] q;
input [1:0] sel;
Register_8bit reg1(
  clk,
  rst,
  d[7:0],
  q[7:0],
  {sel[1], sel[0]}
 );
Register_8bit reg2(
  clk,
  rst,
  d[15:8],
  q[15:8],
 {sel[1], sel[0]}
 );
Register_8bit reg3(
  clk,
  rst,
  d[23:16],
  q[23:16],
 {sel[1], sel[0]}
 );
Register_8bit reg4(
  clk,
  rst,
  d[31:24],
  q[31:24],
 {sel[1], sel[0]}
 );
endmodule
